The performance of a switched capacitor pipeline ADC is very sensitive to (1) mismatch in the capacitors thereof, (2) variation in the finite gain of the operational amplifiers therein, (3) to the accuracy of the reference voltage applied to each stage and (4) charge injection from the switches of the switched capacitor circuitry. Several self-calibration techniques/structures have been described in the prior art.
FIG. 1A shows a 1-bit per stage pipeline ADC of a self-calibrating pipeline ADC described in prior art U.S. Pat. No. 5,499,027 (Karanicolas et al.), with a sample-hold stage 12 followed by N multiply-by-two stages of 14-1, 14-2 etc. Each multiply-by-two stage has an analog input, a one-bit digital input, an analog output, and a one-bit digital output. For example, multiply-by-two stage 14-1 receives analog input 20 and digital input 22, and produces analog output 24 and digital output 26. Multiply-by-two stage 14-2 receives analog input 24 and digital input 26, and produces analog output 24-2 and digital output 26-2. The sample and hold stage and the multiply-by-two stage each utilize a single comparator to generate the respective digital output bits. The digital self calibration circuitry is not shown in FIG. 1A, but is shown in FIGS. 1B and 1C. The quantized representation of Vin is D0, D1, D2 . . . , which is the data word X in FIGS. 1B and 1C.
U.S. Pat. No. 5,499,027 (the ""027 patent) explains that if the residue exceeds the reference boundary due to charge injection offset, comparator offset, or capacitor mismatch, this results in missing decision levels which result in missing codes and consequently in errors in the output word X. The ""027 patent explains that missing codes are caused whenever the output of any stage in a radix 2 pipeline ADC exceeds the reference boundary, and that the gain G should be substantially less than 2 in the stages to be calibrated, in order to prevent the residue from being outside of the reference boundary and causing the missing decision levels and the resulting missing codes.
It should be understood that the Vin vs. Dout transfer characteristic of an ideal pipeline ADC is a straight line. The above mentioned missing codes produce discontinuities in the ideal transfer characteristic so that it is not a straight line. The purpose of the self-calibrating described in the ""027 patent is to xe2x80x9csmooth outxe2x80x9d the discontinuities introduced into the transfer characteristic by the missing codes.
FIGS. 1B and 1C illustrate the recursive self calibration digital logic for calibrating multiply-by-two stage 11 first, and later calibrating MX2 stage 10, etc. The ""027 patent describes pipeline ADC 10 as having the first 11 stages with gains set to 1.93 and the last six stages with gains set to 2. The calibration operation begins by calibrating the 11th stage, and then continues by calibrating the 10th stage, and continuing stage by stage to the first stage 14-1. The gain of 1.93 was chosen to ensure enough gain reduction that the residue never exceeds the reference boundary even in the worst case when the maximum capacitor mismatch, maximum comparator offset, and maximum charge injection error magnitudes are summed together.
In FIG. 1B, the outputs D of xe2x80x9cstage 10xe2x80x9d (not shown) and X of stages 11-17 are provided to digital calibration logic 40 along with stored calibration constants S1 and S2 previously determined and stored for stage 11. S1 and S2 correspond to the values of the data word X when Vin is equal to 0 and D equals 0 and D equals 1, respectively. The digital self calibration process for each stage is described by Y=X if D=0, and Y=X+S2xe2x88x92 S2 if D=1, where D is that the decision, X is the xe2x80x9craw codexe2x80x9d digital output word and Y is the xe2x80x9ctransformed codexe2x80x9d digital output word. S1-S2 is stored for each of the calibrated stages 0-11. To initially determine S1 for stage 11, the analog input is set to 0 and the input bit for stage 11 is forced to 0. The quantity X in this condition is S1 for stage 11, and then the input bit for stage 11 is forced to 1 and in that condition the quantity X is S2 for stage 11.
With the digital calibration of stage 11 accomplished, the digital calibration of the next most significant stage 10 can proceed in the same Fashion, as illustrated by FIG. 1C. Similarly, with the digital calibration of stage 10 accomplished, the digital calibration of the next higher stage 9 can proceed in the same fashion, and so forth all the way to stage 1. Since the digital self calibration aligns the points S1 and S2 using values measured under the same conditions as during the normal conversion, the digital self calibration automatically accounts for capacitor mismatch, charge injection, and finite operational amplifier gain.
It is important to recognize that the switches in blocks 14-1 and 14-2, which function as digital-to-analog converters, operate so as to connect the lower input of each analog summer to either xe2x88x92Vref or +Vref. If the gain of the amplifier 18-1 and amplifier 18-2 is exactly 2 or slightly greater, the self-calibrating ADC xe2x80x9cclipsxe2x80x9d the digital output thereof because the calibrating occurs at a level close to the full scale output value. Stated differently, if the gains of the stages to be digitally calibrated are too close to 2, then the ADC xe2x80x9cover-rangesxe2x80x9d its output. The digitally self calibrated pipeline ADC of the ""027 patent therefore uses a reduced gain of 1.93 for the amplifiers 18-1 and 18-2 and the corresponding amplifiers in all of the self-calibrating stages in order to ensure that the maximum raw digital output value is less than full scale under the worst case condition of maximum capacitor mismatch, maximum comparator offset, and maximum charge injection error magnitude. This enables the self-calibrating ADC of the ""027 patent current to accomplish digital self calibration using subtraction only, which is much less complex than using an adder-subtracter.
Most practical implementations of the pipeline ADC disclosed in the ""027 patent would be fully differential. A major problem with the self-calibrating pipeline ADC of the ""027 patent is that if the differential input signal is very small in magnitude (as often is the case), the worst case transitions from all xe2x80x9c1xe2x80x9ds to all xe2x80x9c0xe2x80x9ds would occur at the zero-crossing points, i.e., at ground or zero volts. The distortions in the digital output signal would be caused by the input offset voltages of the comparators. Such distortions usually would be disproportionately large compared to the amplitudes of the low amplitude differential input signals, and of course, the associated low SNR (signal to noise ratio) would be very undesirable.
The described reduction of the gain G in the ""027 pipeline ADC to a value appreciably less than 2 to avoid clipping of the output caused by over-ranging also can reduce the accuracy of the pipeline ADC, and in fact is likely to prevent the digital output of the pipeline ADC from ever attaining all xe2x80x9c0xe2x80x9ds (and values very close thereto), and also from ever attaining all xe2x80x9c1xe2x80x9ds (and values very close thereto).
Another major problem of the self-calibrating pipeline ADC of the ""027 patent is that the disclosed structure necessarily creates a substantial number of lost digital codes near minimum-scale and full-scale digital outputs. This occurs as a result of the disclosed technique of reducing the gain G of the individual bit stages being self-calibrated, to a value substantially less than 2 in order to avoid clipping of the digital output signal in response to minimum scale and maximum scale values of the analog input signal Vin. This problem can be understood by referring to FIG. 6 of the ""027 patent and associated text. The problem results from the described subtracting technique for subtracting calibration constants from values of the digital output which are shifted due to missing codes that result from major code transitions that cause switching of comparators in the individual bit stages to be calibrated. Further understanding of the problem can be obtained from the subsequent description herein of FIG. 7A.
Another prior art reference is the article xe2x80x9cDigital-Domain Calibration of Multistep Analog-to-Digital Convertersxe2x80x9d, Lee et al., IEEE Journal of Solid-State Circuits, Volume 27, Number 12, December 1992. The Lee article describes a digital self-calibration technique which can directly cancel code errors in xe2x80x9cmultistep conversionsxe2x80x9d. The described digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated xe2x80x9crawxe2x80x9d digital outputs. The article explains that the conversion rate of a flash ADC is inherently the fastest of all the existing ADC topologies, but the flash ADC suffers from requiring larger chip area, higher power dissipation, and high input capacitance. The Lee article explains that a multistep or pipeline ADC employs a fully serial approach with two or more stages. Each stage consists of a sample-and-hold amplifier (S/H), a low-resolution flash ADC, a DAC, and a residue amplifier, and that the primary advantages of the multistep or pipeline ADC are its high throughput rate due to the concurrent operation of the stages and its considerable reduction in area and power consumption. The Lee article also explains that the digital code-error calibration technique is applied to improve the linearity of this ADC by directly measuring and canceling cumulative code errors resulting from the capacitor ratio mismatch as well as from other non-linearity errors of the MDAC.
The Lee article discloses a digital self-calibrating, recycling two-step ADC whose linearity relies on matching the accuracy of capacitors in of a binary-weighted capacitor array. The two-step ADC uses an MDAC that performs the triple functions of a sample and hold circuit, a DAC, and a residue amplifier. The digital code-error calibration technique is applied to improve the linearity of this two stage ADC by directly measuring and canceling cumulative code errors resulting from capacitor ratio mismatches and other non-linear errors of the MDAC. The Lee article explains that the overall ADC linearity is limited by the mismatch of components at major code transition points, and that if less significant digital output codes are grouped as segments and each segment is dislocated by a certain amount from the ideal straight line of a plot of digital output vs. analog input, the digital amounts of dislocation measured from the ideal line are defined as xe2x80x9ccode errorsxe2x80x9d, and that each dislocated segment can be moved back to the straight line by digitally subtracting the amount of dislocation from each digital output occurring in that range. The amounts of dislocation are directly measured during a calibration measurement cycle and stored in memory. The code errors are later addressed and recalled using coarse digital outputs from the first stage of flash ADC. The uncalibrated ADC produces raw digital data with a limited linearity during normal conversion, and the code error calibration is done with the raw digital data after the normal conversion is completed.
The described two-step ADC includes an input buffer amplifier, an MDAC, a flash ADC, digital correction and calibration logic, a binary encoder, memory, and digital control logic. The three clock phases are used so that the same flash converter can be used repeatedly for both the coarse and fine conversions. During the first clock phase, the input is sampled on the bottom plates of the MDAC capacitor array. During the second clock phase, the sampled and held input voltage is converted into xe2x80x9ccoarsexe2x80x9d N+1 bits employing the flash ADC. These coarse N+1 bits are stored in the digital correction logic, and a voltage corresponding to the coarse N+1 bits is reconstructed using an (N+1)-bit DAC. During the third clock phase a residue voltage, which is the difference between the sampled and held input and the reconstructed output of the (N+1)-bit DAC, is amplified by 2N and fine N+1 bits are obtained using the same flash ADC structure. The residue amplifier output should change by exactly half of the reference voltage Vref when the digital input code changes by 1. The xc2xdVref value results from two unit feedback capacitors of the MDAC during the residue amplification phase which reduces the residue voltage by half. Code-error measurements begin by measuring the feedback error on the top plate of the MDAC capacitor array. During the first clock phase, a code Dj is applied to the MDAC switches connecting the bottom plates of the binary-weighted capacitors to either Vref or ground, while the top plate samples the operational amplifier offset voltage. At the same time, the bottom plate of the feedback capacitor 2C is connected to ground. During the next clock phase, the feedback capacitor is connected to the operational amplifier feedback V0 while the bottom plates of the remaining capacitors remain unswitched. After charge redistributions, the feedthrough voltage VFT is generated at the operational amplifier output and digitized using the flash ADC. After the feedthrough voltage measurement, the segment error between two adjacent codes, Dj and Dj+1, is similarly measured. Vref and the feedthrough voltage VFT is subtracted from the digitized outputxe2x80x94xc2xdVref, which is the error of the segment between the input codes Dj and Dj+1. The same procedure is repeated until all segment errors are measured. During normal conversion, coarse N+1 and fine N+1 bits are obtained. The coarse (N+1)-bit output is used as an MDAC code-error address. The fine N+1 bits are generated by digitized in an amplified residue voltage from the MDAC. The (N+1)-bit code error, which is stored in memory, is subtracted from the uncalibrated (2N+1)-bit digital output.
There is an unmet need for an integrated circuit self-calibrating pipeline ADC which avoids missing codes near maximum-full-scale and minimum-zero-scale values of the digital output.
There also is an unmet need for a differential integrated circuit self-calibrating pipeline ADC wherein high signal-to-noise ratio near the zero-crossing point of the digital output is obtained.
There also is an unmet need for an integrated circuit self-calibrating pipeline ADC having, a maximum dynamic range of its digital output and also having a high signal-to-noise ratio near zero-crossing point values of its digital output.
Accordingly, it is an object of the invention to avoid high distortion at zero-crossing points of a self-calibrating differential pipeline ADC.
It is another object of the invention to provide a self-calibrating pipeline ADC which avoids lost codes near maximum-full-scale digital output and/or minimum-full-scale values of the digital output.
It is another object of the invention to provide a self-calibrating pipeline ADC in which it is not necessary to provide a reduced gain of less than 2 in the individual stages to be calibrated in order to avoid clipping the digital output signal at values close to the minimum-full-scale or maximum-full-scale values of the digital output from.
It is another object of the invention to provide a self-calibrating pipeline ADC having a higher signal-to-noise ratio than can be achieved using the structure disclosed in prior art U.S. Pat. No. 5,499,027.
It is another object of the invention to provide a self-calibrating pipeline ADC having a is higher dynamic range of its digital output signal than can be achieved using the structure disclosed in prior art U.S. Pat. No. 5,499,027.
It is another object of the invention to provide a self-calibrating, differential pipeline ADC having both a high dynamic range of its digital output signal and low signal distortion, especially for low-magnitude analog input signals, and also having a high signal-to-noise ratio for low-magnitude analog input signals.
It is another object of the invention to provide a self-calibrating pipeline ADC in which the dynamic range of the digital output is not highly sensitive to the gain of the individual bit stages to be calibrated.
Briefly described, and in accordance with one embodiment thereof, the invention provides a pipeline ADC including a plurality of stages including an input stage (12) and a first group of subsequent stages (14-1,2 . . . ), wherein the input stage (12) includes a unity gain amplifier (16) having an input for receiving an analog input signal (Vin), an output (20), and first (17A) and second (17B) comparators each having a first input coupled to the output (20) of the unity gain amplifier (16). The first comparator (17A) has a second input for receiving a first reference voltage (xe2x88x92xc2xcVref) an first output (22A), and the second comparator (17A) has a second input for receiving a second reference voltage (+xc2xcVref) and an output (22B). The input stage includes a full adder (40A) having a first input coupled to the output (22A) of the first comparator (17A), a second input coupled to the output (22B) of the second comparator (17B), and an output (A14, A11) producing MSB bit information. Each subsequent stage (14-1,2, . . . ) includes an amplifier (18-1,2 . . . ) of gain greater than 2 having an input and an output, a summer (15-1,2 . . . ) having a first input coupled to the output of the amplifier of gain greater than 2, a second input, and an output (24-1,2 . . . ), a switching circuit (28-1,2 . . . ) operating in response to the outputs of the first and second comparators of a previous stage to selectively couple one of a third reference voltage (xe2x88x92Vref), a fourth reference voltage (GND), and a fifth reference voltage (+Vref) to a second input of the summer (15-1,2 . . . ). Each subsequent stage also includes a full adder (46-1,2 . . . ) having a first input coupled to the first output (26-2A), a second input coupled to the second output (26-1B). The full adder (46-1,2 . . . ) produces bit information less significant than the MSB bit information. In the described embodiments, the third reference voltage is a negative reference voltage (xe2x88x92Vref) the fourth reference voltage is a ground reference voltage, the fifth reference voltage is a positive reference voltage (+Vref). The first reference voltage is midway between the third reference voltage and the ground reference voltage, and the second reference voltage is midway between the ground reference voltage and the fifth reference voltage. Each switching circuit (28-1,2 . . . ) operates to decode one of three states represented by the first (17A) and second (17B) comparators of the previous stage. The plurality of stages include a second group of subsequent stages of lower binary bit significance than the first group of subsequent stages, the first group of subsequent stages being recursively self-calibrated, the second group of subsequent stages being not self-calibrated.
In the described embodiment, the pipeline ADC is a self-calibrating pipeline ADC including a plurality of analog-to-digital conversion units and a recursive calibrating section (32,14-5,41,40A-D of FIG. 6) operable for calibrating errors associated with an immediately preceding first conversion unit (14-4 of FIG. 6). The recursive calibrating section includes a first circuit for receiving an analog output signal (24-4 of FIG. 6) generated from the first conversion unit (14-4) in response to an analog input signal (24-3) provided to the first conversion unit, a second circuit (28-5) for receiving a digital output signal (26-4A,26-4B) generated from the first conversion unit (14-4) in response to a digital input signal (26-3A,26-3B) provided to the first conversion unit (14-4), a third circuit (41,32 of FIG. 6) for generating a conversion signal (X) corresponding to a quantized representation of the analog output signal (24-4 of FIG. 6), and a fourth circuit (40A-D of FIGS. 5 and 6) for generating a calibration signal (Y) having a value equal to the conversion signal (X) in response to the digital input signal being a first digital value (xe2x80x9c0xe2x80x9d) and having a value equal to the sum of the conversion signal (X) and a calibration value (S1-S2 or S3-S4) in response to the digital input signal being a second digital value (xe2x80x9c1xe2x80x9d).